The present invention relates to an apparatus and method for cache coherency by detecting snoop hits on victim lines issued to a higher level cache in a multiprocessor system.
In a multiprocessor system, each processor has its own local cache for storing data. Each processor may write to and read from a shared higher-level cache. Therefore, each processor can access both its own local cache and the shared cache for the entire system. Cache coherency is required to ensure that two processors do not attempt to simultaneously access the same address space of the shared cache. In addition, due to propagation delays within the circuitry of each processor, cache coherency must ensure that attempts to access particular portions of a cache are prioritized.
In particular, when a processor attempts to replace a line in its local cache, it sends a victim address to its victim buffer in order to victimize an address space. At the same time, it transmits the victim address to a bus cluster, which is an internal on-chip interface between the processor and a system bus. The bus cluster manages prioritization of attempts to access the cache. Due to a propagation delay, the victim address transmitted to the bus cluster may require, for example, two clock cycles to reach the bus cluster. During those two clock cycles, another processor may attempt to access the same address space in the shared cache. If that occurs, the bus cluster will not be aware of the conflict resulting from attempts by both processors to access the same portion of the shared cache due to the two clock cycle delay. Therefore, circuitry must account for this type of conflict. In particular, a need exists for detecting snoop hits occurring on the same address space during a propagation delay when transmitting a victim address from a processor to a bus cluster in order to avoid conflicts while accessing the cache.
A method and apparatus consistent with the present invention includes receiving a victim address for a local cache in a multiprocessor system and transmitting the victim address to a bus cluster interfacing a processor with a system bus. A snoop is received during transmission of the victim address to the bus cluster, and it is determined if the snoop hits the victim address. If the snoop hits the victim address, a unique snoop hit signal is provided.
Another apparatus consistent with the present invention includes a plurality of wordlines corresponding to a victim address that was sent to a bus cluster and a snoop match line for detecting a snoop hit. Logic circuitry, connected to the plurality of wordlines and the snoop hit line, operates to determine if the snoop hit relates to the victim address that is being transmitted to the bus cluster interfacing a processor with a system bus. The logic circuitry also operates to provide a snoop hit signal if the snoop hits a victim address stored in the victim buffer and not yet issued to the bus cluster.